There are a variety of competing modulation techniques for wideband communications, including, for example, Phase Shift Keying (PSK), Amplitude Shift Keying (ASK), Quadrature Amplitude Modulation (QAM), and variations of each, to name a few. There is an increasing need for communication transmitters and receivers that can process and code/decode more than one modulated waveform. For example, various U.S. Government agencies communicate using Common Data Link Class 1 category A and B waveforms, Terrestrial Line of Sight waveform, classified direct downlink waveform, numerous waveforms for civil and military communications with satellites and/or military assets, and the (to be determined) commercial teledesic waveform. Overlap between these agencies, and between arms of other governments or multinational corporations that communicate over numerous disparate systems, is beginning to drive a need for flexible-modulation hardware that can operate among various communications waveforms such as those above.
One approach in achieving the above hardware flexibility is a modem that is programmable for any particular modulation. Such a modem is termed a programmable digital modem, which forms a key component of software-defined radios. Two related components of such a modem are filters, especially pulse shaping filters that upsample an input signal during each symbol, and up-converters for converting the shaped signal from a baseband frequency to an intermediate frequency (IF). On the demodulate side, the reverse functions are required. Wideband programmable modems by necessity incorporate field programmable gated arrays (FPGAs) and/or digital signal processors (DSPS) as opposed to application specific integrated circuits (ASICs) that are typically used in modems dedicated to a particular modulation scheme. Clock speeds in FPGAs are generally slower than those in ASICs, so at least the first generation of software-defined radios are expected to operate at maximum clock speeds in the range of 100 to 300 MHz.
In general, a signal input into a modulator is up-sampled at some integer multiple of the symbol rate (the sampling frequency) for pulse shaping and up-conversion to an intermediate frequency (IF). Except for spread spectrum systems, pulse shaping is desirable to compress the bandwidth of data impulses without increasing intersymbol interference (ISI) inordinately. For most applications, proper pulse shaping requires three or four samples per symbol, and up-conversion occurs at the data rate output from the pulse-shaping filter. Many prior art systems are designed to avoid intersymbol interference (ISI). For prior art systems wherein the sampling frequency is limited to the clock speed, then upsampling three times per symbol yields a symbol rate of about one third the clock speed. Considering the FPGA clock speeds noted above, this prior art limitation on data rate is unacceptable for wideband programmable modem applications. Software defined radios with low data rates are currently available. The present invention is directed to meeting the challenge of enabling high data rates for wideband programmable modems.
Prior art systems for sampling and up-conversion are shown generally in FIGS. 1 and 2. FIG. 1 is a block diagram showing an in-phase signal I, and a quadrature signal Q that is orthogonal to the in-phase signal. Each of the I and Q signals are up-sampled at three times the symbol rate in the embodiments of FIG. 1, producing 3 samples per symbol that are input into a digital pulse shaping filter 12, such as a Nyquist filter. The output of the filter 12 is at the same rate as its input, 3 samples per symbol. This output enters a multiplier 14, where the I signal is modulated onto an up-converted cosine signal 16 and the Q signal is modulated onto an up-converted sine signal 18. The term fIF is the up-converted frequency and the term tn is the nth sample equal to nTs, where Ts=1/fs is the sampling period. The modulated orthogonal signals enter an adder 20 and are output as a combined digital signal 22, which is typically input into a digital to analog converter (DAC) and transmitted.
Assuming, for example, that a device system clock of FIG. 1 is running at fclk=200 MHz, then the sample rate fs is limited to 200 Msps (million samples per second), and the symbol rate in the above example is limited to 200/3 million symbols per second. One drawback to the design of FIG. 1 is that the filter 12 has to run at the sample rate operating on the zeros inserted by the up-sampler 10. To eliminate this inefficiency, the prior art may employ a polyphase filter structure such as that shown in FIG. 2.
In the prior art circuit of FIG. 2, each I and Q input signal is split to enter a plurality i of polyphase components Hi(z) [depicted as H1(z), H2(z), H3(z)] of a polyphase filter 24. The depicted filter 24 up-samples by three and pulse shapes the complex signal, but not all polyphase components run at the same time. At any time instant n, only the ith polyphase component on each I and Q line is generating an output. At time n+1, the polyphase component with index (i+1) modulo 3 generates an output. The two portions of the gate 26 operate in tandem to select corresponding I and Q samples from the corresponding polyphase components Hi(z). As with FIG. 1, the I and Q pulses each enter a multiplier 14, are modulated and up-converted on a cosine 16 and sine 18 carrier wave, and added at an adder 20 to produce a combined digital signal 22 for output to a multiplexer, digital to analog converter, or other circuitry. The architecture of FIG. 2 saves on multipliers as compared to FIG. 1, since each polyphase component Hi(z) of the polyphase filter 24 is one-third the order of the pulse-shaping filter 12 of FIG. 1. Despite this computational efficiency, the circuit of FIG. 2 remains limited to a symbol rate of one-third the system clock (system clock divided by the up-sampling factor), just as the circuit of FIG. 1. In each of FIGS. 1 and 2, it is assumed that the sine and cosine functions are generated by a numerically controlled oscillator (not shown) runmning at the sample rate fs.